1
FN6810.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5610P
Dual 10-Bit, 250/210/170/125MSPS A/D
Converter
The KAD5610P is a family of low-power, high-performance,
dual-channel 10-bit, analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge technology on a
standard CMOS process, the family supports sampling rates
of up to 250MSPS. The KAD5610P-25 is the fastest member
of this pin-compatible family, which also features sample
rates of 210MSPS (KAD5610P-21), 170MSPS
(KAD5610P-17) and 125MSPS (KAD5610P-12).
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of gain, skew and offset
matching between the two converter cores.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5610P is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
Features
Programmable Gain, Offset and Skew control
1.3GHz Analog Input Bandwidth
60fs Clock Jitter
Over-Range Indicator
Selectable Clock Divider:
÷1, ÷2 or ÷4
Clock Phase Selection
Nap and Sleep Modes
Two’s Complement, Gray Code or Binary Data Format
DDR LVDS-Compatible or LVCMOS Outputs
Programmable Built-in Test Patterns
Single-Supply 1.8V Operation
Pb-Free (RoHs Compliant)
Applications
Power Amplifier Linearization
Radar and Satellite Antenna Array Processing
Broadband Communications
High-Performance Data Acquisition
Communications Test Equipment
WiMAX and Microwave Receivers
Key Specifications
SNR = 60.7dBFS for fIN = 105MHz (-1dBFS)
SFDR = 86.1dBc for fIN = 105MHz (-1dBFS)
Power Consumption
- 411mW @ 250MSPS
- 327mW @ 125MSPS
DIGITAL
ERROR
CORRECTION
SHA
1.25V
AINP
AINN
10-BIT
250MSPS
ADC
SHA
BINP
BINN
10-BIT
250MSPS
ADC
VREF
CLKP
CLKN
SPI
CONTROL
CS
B
SC
LK
SDIO
VREF
OV
S
AV
S
AVDD
CLKOUTP
CLKOUTN
D[9:0]P
D[9:0]N
ORP
ORN
OUTFMT
OUTMODE
OVDD
CLKDI
V
NAP
SL
P
SDO
+
RE
S
E
TN
VCM
CLOCK
GENERATION
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
KAD5612P-25
12
250
KAD5612P-21
12
210
KAD5612P-17
12
170
KAD5612P-12
12
125
KAD5610P-25
10
250
KAD5610P-21
10
210
KAD5610P-17
10
170
KAD5610P-12
10
125
Data Sheet
September 10, 2009
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